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Changelog

All notable changes to this project will be documented in this file.

The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.

[Unreleased]

Changed

  • Reorganize code for better decomposition, encapsulation, stricter API and easier maintenance and development
  • Start using pydantic for all internal data models
  • Reorganize CLI into commands via typer
  • Switch to YAML for a build specification (former csrconfig) (#81)
  • Switch to modern python infrastructure for linting and package management (uv, ruff, pyright)
  • Rework CI to run jobs inside devcontainer
  • Switch to MkDocks-Material for documentation rendering
  • Switch to Github Pages for documentation hosting
  • Start following Conventional Commits specification for commit messages
  • Start following Keep a Changelog specification for changelog (#82)

Added

  • Git pre-commit hooks via pre-commit tool
  • Docker image with development workspace including Verilator and Modelsim
  • Devcontainer config to facilitate workspace deployment and IDE use
  • Cursor rules to facilitate using of LLMs via Cursor
  • Package features management to avoid installing unnecessary dependencies (e.g. hjson, wavedrom)
  • CLI command corsair check to validate input files
  • CLI command corsair schema to generate JSON-schemas of input files for IDE hints, autocompletion and validation
  • CLI command corsair build to render outputs
  • CLI command corsair init to initialize a new project
  • BuildSpecification data model to store build targets and configuration
  • Register map data models (Map, Register, Field, Enum, EnumMember) for internal CSR representation
  • SetializedParser to parse register map from JSON/YAML/HJSON files
  • WavedromGenerator to generate SVG images of bitfields
  • MarkdownGenerator to generate Markdown document for a register map

Removed

  • Corsair 1.x source code, documentation, examples

[1.0.4] - 2023-03-17

Fixed

  • rolh/roll missing latch bug.
  • Constants comparison on address in VHDL.
  • C/C++ header generation.

[1.0.3] - 2023-03-06

Fixed

  • Various bug fixes.

[1.0.2] - 2021-09-26

Fixed

  • Overlapping of bitfield names in rendered images for registers.

[1.0.1] - 2021-09-08

Fixed

  • Issue where the input globconfig file was not being applied to generators.

[1.0.0] - 2021-09-03

Added

  • New configuration file format (INI).
  • New file generation flow.
  • Enums.
  • C header generator.
  • Verilog header generator.
  • SystemVerilog package generator.
  • Bus interface embedding (AXI-Lite, APB, Avalon-MM) into a register map.
  • VHDL register map generator.
  • Plenty of examples.

Changed

  • Reworking the entire project almost from scratch. Lots of breaking changes.
  • Refactoring of all core modules.
  • Rework of documentation.
  • Update the tests.
  • Many minor tweaks and fixes.

[0.3.0] - 2021-02-21

Added

  • 'Reserved' bitfields to Markdown.
  • access_strobes attribute for register.
  • Complementary registers.
  • write_lock attribute for register.
  • FIFO bitfield modifier.
  • AXI-Lite to Local Bus bridge on Verilog.
  • Avalon-MM to Local Bus bridge on Verilog.

Fixed

  • Markdown table row endings.
  • Installation guides.

[0.2.0] - 2021-01-08

Added

  • Verilog and Markdown writers for a register map.
  • Local Bus bridge writer.
  • APB to Local Bus bridge on Verilog.
  • HDL testing environment.
  • CI/CD via Github Actions.

Changed

  • Rework CLI keys.
  • Documentation fixes, code prettifying and etc.

Fixed

  • Entry point for CLI.

[0.1.0] - 2020-12-16

Added

  • Setup repository.
  • Setup documentation.
  • Setup testing.
  • Implementation of core classes.
  • Support for running from a command line.
  • JSON and YAML readers.
  • JSON and YAML writers.